【Group./Dept.】CPU Platform
【Responsibilities】
This person will lead a team of engineers. The main charter for this group is responsible for IC Front-end design and verification flow. The manager will develop and maintain s<x>cripted flows and methodologies to improve RTL to GDS design productivity in the following areas: logic synthesis/physical synthesis, DFT, static timing analysis, function verification, power consumption optimization, etc. Also, define and maintain the state-of-art verification environment using the latest verification methodology.
1. ASIC design flow and methodology development for RTL-to-GDS implementation;
2. Verification plan, strategy, methodology and implementation;
2. New EDA tool evaluation;
3. Intenal s<x>cript development, utilizing Perl, TCL and C-Shell;
4. Maintenance and enhancement of internal tools.
【Requirements】
1. Master degree in Electrical Engineering, Computer Science/Engineering, or related engineering fields with 4+ years of related working experiences;
2. Strong Verilog coding experience;
3. Strong verbal communication and interpersonal skills to work closely with a variety of individual contributors and managers;
4. Team work spirit;
5. Good spoken and written English skills;
6. The following items are plus:
a) Experienced in commercial EDA tools (e.g., Synopsys, Cadence, Mentor, Magma etc)
b) Experience on RTL design
c) Tcl/TK, C- Shell, Perl, SystemVerilog
d) Technical expertise in one of the following areas are preferred: VLSI technologies, IC design flow, design for manufacturability (DFM)
